1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular, relates to an overdrive write method in which a write operation is performed by an overdrive method, a write amplifier power generating circuit, and a semiconductor memory device that includes the same.
2. Description of the Related Art
In recent semiconductor memory devices, high-speed processing and low power consumption are achieved. A typical method for achieving high-speed processing and low power consumption is the Boosted Sense Ground (BSG) method. In the BSG method, internal voltages VDL and VSL are used as the high and low levels of bit line read signals. The internal voltage VDL is lower than a power supply voltage VEXT supplied from an external source by a predetermined amount, and the internal voltage VSL is higher than a ground voltage GND by a predetermined amount. The internal voltage VDU the internal voltage VSL is supplied as a power supply voltage of an internal circuit in which the BSG method is adopted. The internal voltage VDL/the internal voltage VSL is smaller than the power supply voltage VEXT/the ground voltage GND. Thus, the signal amplitude in an internal circuit that includes a complementary metal-oxide semiconductor (CMOS) is also the internal voltage VDL/the internal voltage VSL. Low power consumption is achieved by operating an internal circuit with a low voltage in this way, and moreover, high-speed data transfer is achieved by suppressing noise by a small signal amplitude.
However, in the BSG method, although high-speed data transfer is achieved by a small signal amplitude, a problem exists in that a restore operation of a cell is slow. Thus, an overdrive sense method is adopted. In the overdrive sense method, a power supply voltage applied to a sense amplifier is increased at the beginning of a restore operation of a cell. Moreover, in a write operation, when the amplitude of an input signal is small, the capability in inverting a bit line pair falls short, and thus the write time gets longer. Thus, even when a write operation is performed, the overdrive method is used. In the overdrive method, the power supply voltage VEXT and the ground voltage GND are supplied.
Some types of overdrive method are described in, for example, International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470. General overdrive methods described in International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470 will now be described. In the description of International Publication No. WO97/24729, a power supply voltage VEXT and a ground voltage GND are supplied as operating power supplies for a sense amplifier at the beginning of a sensing operation. After sensing and amplification operations are quickly performed, internal voltages VDL and VSL are supplied. In the description of Japanese Unexamined Patent Application Publication No. 10-255470, a power supply voltage VEXT and a ground voltage GND are supplied as operating power supplies for a write amplifier only for a predetermined period. After a sense amplifier is rapidly inverted, the operating power supplied for the write amplifier are internal voltages VDL and VSL.
In a write operation by the overdrive method described in Japanese Unexamined Patent Application Publication No. 10-255470, the high and low levels of write signals from a write amplifier WAMP are the power supply voltage VEXT and the ground voltage GND for the predetermined period until voltages of a bit line pair cross each other. After the predetermined period, the high and low levels of write signals are changed to the internal voltages VDL and VSL so that the level to be written to a memory cell and the signal levels in a pair of complementary bit lines BIT T and BIT N are the internal voltages VDL and VSL. In this way, the substantial achieved amplitude of write signals in the pair of the complementary bit lines BIT T and BIT N is set so as to be larger than the achieved amplitude of amplified read signals in the pair of the complementary bit lines BIT T and BIT N, and a write operation by the overdrive method is performed.
However, the inventor found that a problem existed with these overdrive write methods in the case of successive write operations. The problem is that, when successive write operations are repeated on the same word line, a bit line voltage may be excessively boosted. In this case, an overdrive operation is performed, with the power supply voltage VEXT (VDD), which is higher than the internal voltage VDL, on bit lines in which sufficient voltage difference is generated by performing amplification on the basis of data stored in a memory cell. In this way, when an overdrive operation is repeated, the bit line voltage is excessively boosted. This is because the power supply voltage VEXT from a write amplifier, which is higher than the internal voltage VDL, is supplied to the bit lines via an input/output (IO) data line and a column selection switch.
For example, in general, an IO data line and a bit line are connected by a column selection switch YSW that includes an N-channel transistor. The power supply voltage VEXT is applied as the gate voltage of the column selection switch YSW. When the high level of the IO data line is also the power supply voltage VEXT, VEXT−Vtn is applied to the bit line. When successive write operations are performed, in one of the complementary bit lines, the voltage is excessively boosted, so that the voltage is equal to or higher than the internal voltage VDL. When a precharge operation is performed, after the bit line voltage is excessively boosted, a correct reference level cannot be obtained. The precharge operation is performed to charge the complementary bit lines to a reference level (VDL/2).
Thus, in order to obtain a correct reference level in the overdrive write method, the voltage level of the bit line needs to be decreased to the VDL level so as to prevent the voltage from being excessively boosted. Alternatively, the overdrive write method may not be performed so that the output level of the write amplifier is set to the internal voltage VDL. However, when a write operation is performed using the internal voltage VDL, high-speed processing is adversely affected. At the beginning of a sensing operation by a sense amplifier, a high voltage (VEXT) is supplied to the sense amplifier. It takes long time for the sense amplifier operating with the high voltage (VEXT) to invert and write data at the internal voltage VDL, which is lower than the high voltage (VEXT). When a high-speed write operation needs to be performed at the internal voltage VDL, a power supply for a write circuit that has a large charge capacity is necessary. Thus, the power supply for a write circuit needs a large compensation capacitance, thereby adversely affecting a reduction in the chip size, and the power efficiency.
The problem will now be described in detail with reference to FIGS. 1 to 6. FIGS. 1 and 2 are a first schematic block diagram of a semiconductor memory device and a second schematic block diagram of another semiconductor memory device, respectively. FIG. 3 is a circuit diagram of a write amplifier (WAMP). FIG. 4 is a circuit diagram of a sense amplifier (SA) and a column selection switch (YSW). FIG. 5 is a circuit block diagram for illustrating a write operation. FIG. 6 is a timing chart of a write operation by a known overdrive write method.
In the semiconductor memory device shown in FIG. 1, memory cells are disposed in the form of a matrix in a memory cell array 1 surrounded by a word driver row (WD) 2 and a sense amplifier row (SA) 3. The sense amplifier row (SA) 3 includes a plurality of sense amplifiers. Each of the sense amplifiers is selected according to a column selection signal YSW. A selected sense amplifier is connected to a write amplifier (WAMP) and a data amplifier (DAMP) 6 (hereinafter called a write amplifier WAMP 6) via a pair of complementary IO data lines IO T and IO N. Hereinafter, a word driver row and a word driver are not distinguished, and both of them are called a word driver (WD) 2. A sense amplifier row and a sense amplifier are not distinguished, and both of them are called a sense amplifier (SA) 3.
The second schematic block diagram in FIG. 2 shows the other semiconductor memory device that includes a plurality of memory cell arrays. When a plurality of blocks of memory cell arrays exist, data lines are stratified and connected to the write amplifier WAMP 6. A pair of bit lines BIT T and BIT N in a memory cell array is selected by a column selection switch YSW and connected to a pair of complementary IO data lines IO T and IO N. Moreover, the pair of the complementary IO data lines IO T and IO N is selected by an IO selection switch 5 and connected to the write amplifier WAMP 6. A current semiconductor memory devices includes a plurality of memory cell arrays, and the data lines are stratified. However, the essence of the present invention does not relate to the stratification of data. Thus, in the following description, the schematic block diagram in FIG. 1 is used.
In the write amplifier (WAMP) 6 in FIG. 3, when a write enable signal WAE is at the high level, data in a read write bus RWBS is output to a pair of complementary IO data lines IO T and IO N. The power supply voltage of an output driver of the write circuit is VRW, and the high and low levels of data are VRW and GND. In a general overdrive write method, VRW is an external power supply voltage VEXT supplied from an external source. It does not matter whether the data in the read write bus RWBS is complementary data.
Write data from the write amplifier WAMP 6 is transferred to the pair of the complementary IO data lines IO T and IO N, as shown in FIG. 4. Moreover, the write data is transferred to a pair of bit lines BIT T and BIT N via a column selection switch YSW 4 and written to the sense amplifier (SA) 3 and a selected memory cell. The sense amplifier (SA) 3 is a flip-flop circuit that includes two inverter circuits and is connected to the pair of the bit lines BIT T and BIT N. A high power supply voltage (SAP)/a low power supply voltage (SAN) is supplied to the sense amplifier (SA) 3. As the power supply of the sense amplifier (SA) 3, the external power supply voltage VEXT/the ground voltage GND is supplied during an overdrive period at the beginning of a sensing operation, and an internal voltage VDL/an internal voltage VSL is supplied during a regular operation period. When the sense amplifier (SA) 3 is not activated, the power supply voltages are not supplied.
The column selection switch YSW 4 includes an N-channel transistor and is selected according to the selection signal YSW and brought into conduction. When the column selection switch YSW 4 is brought into conduction, data in the pair of the complementary IO data lines IO T and IO N is transferred to the pair of the bit lines BIT T and BIT N, respectively. The data levels from the pair of the complementary IO data lines IO T and IO N are the high level VRW and the low level GND, which are the signal levels of an output stage of the write amplifier WAMP 6.
The problem with successive write operations will now be described with reference to FIGS. 5 and 6. The write amplifier WAMP 6 outputs write data to the complementary IO data lines IO T and IO N. In the case of the overdrive write method, the power supply voltage VEXT is supplied as the power supply VRW of the write amplifier WAMP 6. A sense amplifier power circuit 7 generates the power supply voltage SAP/the power supply voltage SAN of the sense amplifier (SA) 3. The power supply voltage VEXT is supplied from an external source. The internal voltage VDL is an array voltage and is lower than the power supply voltage VEXT. The sense amplifier power circuit 7 supplies the power supply voltage to the common source power supply SAP/SAN of the sense amplifier (SA) 3 according to a sense amplifier enable signal SE.
A path exists for supplying the power supply voltage VEXT to the common source power supply SAP of a high voltage according to a sense overdrive signal (ODV or ODV2) during an overdrive period at the beginning of a sensing operation. A small voltage difference from the charge from a memory cell is sensed at the beginning of a sensing operation. In this case, in order to turn on a P-channel transistor in the sense amplifier (SA) 3, a high voltage is necessary as the high voltage power supply SAP. The high voltage exceeds a threshold voltage Vt of the P-channel transistor from the reference level of the internal voltage VDL/2. The high voltage power supply SAP is overdriven to be set to the power supply voltage VEXT to obtain the high voltage. After row address strobe (RAS) to column address strobe (CAS) delay (tRCD) LONG, i.e., after sufficient time has elapsed since the beginning of a sensing operation, amplification in the bit lines BIT T and BIT N by the sense amplifier (SA) 3 is almost completed, and the high voltage power supply SAP is again set to the VDL level, which is a predetermined voltage.
Various types of overdrive method exist for boosting the high voltage power supply SAP. For example, a type of overdrive method exists, in which the power supply voltage VEXT is connected to the sense amplifier power circuit 7 in FIG. 5 according to a sense overdrive signal (ODV2), as indicated by a dotted line. Moreover, another type of overdrive method exists, in which a node VDL of a VDL power circuit is overcharged according to a sense overdrive signal (ODV), and the voltage is supplied as the high voltage power supply SAP according to the sense enable signal SE. In the description of the present invention, the other type of overdrive method is used, in which an overcharge operation is performed. The write amplifier WAMP 6 has the circuitry shown in FIG. 4, and the power supply voltage VRW of the output driver is the power supply voltage VEXT supplied from an external source. Thus, the high and low levels of write data are VEXT and GND.
FIG. 6 shows the waveforms of successive write operations in the case of the tRCD LONG. FIG. 6 shows the waveforms of a word line WL, the sense overdrive signal ODV, the sense enable signal SE, a write enable signal WAE, column selection switches YSW, the node VDL, and the pair of the bit lines BIT T and BIT N. The node VDL is a node of the sense amplifier power circuit 7, which generates a voltage to be supplied to the high voltage common source SAP of the sense amplifier (SA) 3. When a selected word line is activated, a small voltage difference in a memory cell is detected in the pair of the bit lines that are precharged to the reference level VDL/2. The node VDL is overcharged according to the overcharge signal ODV.
A voltage is applied to the common source of the sense amplifier (SA) 3 according to the sense enable signal SE. At the beginning of a sensing operation, an overdrive operation is performed so that the power supply voltage VEXT is applied to the high voltage power supply SAP. The power supply voltage VEXT is higher than the internal voltage VDL. Thus, a sensing operation is performed quickly. FIG. 6 shows parts (indicated by full lines) of the pair of the bit lines BIT T and BIT N near the sense amplifier (SA) 3 and other parts (indicated by dot lines) of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3. When amplification is almost completed in the parts of the pair of the bit lines BIT T and BIT N near the sense amplifier (SA) 3, the voltages of the node VDL and the high voltage power supply SAP are again set to the internal voltage VDL. Then, amplification is completed in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3.
Then, when the write enable signal WAE is activated, successive write operations are performed by the overdrive write method. The voltage VRW (in this case, VEXT), which is higher than the internal voltage VDL, and the ground voltage GND are respectively output as the high and low levels of write data from the write amplifier WAMP 6. When one of the column selection switches YSW selected according to the column selection signal is brought into conduction, write operations are performed on the sense amplifier (SA) 3, the pair of the bit lines BIT T and BIT N, and the memory cell. In this case, since the high level of the column selection signal is also the power supply voltage VEXT, a voltage of VEXT−Vtn is applied to a bit line. The voltage in the bit line is excessively boosted from the internal voltage VDL to VEXT−Vtn.
Since no path exists for discharging the charge, the more times successive write operations are performed, the more excessively the voltage in the bit line is boosted. The high voltage power supply SAP of the sense amplifier (SA) 3 is also boosted. In this way, the voltage in the bit line and the high voltage power supply SAP of the sense amplifier (SA) 3 are boosted from the internal voltage VDL to VEXT−Vtn. In FIG. 6, when the column selection switches YSW are sequentially selected and when the number of times successive write operation are performed increases, the voltage is boosted. When successive write operations are performed n times, the voltage is boosted to VEXT−Vtn. In this way, the bit line voltage is excessively boosted, so that the voltage in one of the complementary bit lines is boosted to VEXT−Vtn.
In a status in which the voltage in one of the complementary bit lines is boosted to VEXT−Vtn, write operations are completed, and a precharge operation is performed. However, since a precharge circuit does not include any path for discharging the charge, the voltage is excessively boosted to a voltage level that is equal to or more than the internal voltage VDL. In this status, in a precharge operation in which complementary bit lines are shorted, the reference level is set to a voltage level that is equal to or more than VDL/2. Thus, a correct reference level (VDL/2) cannot be obtained. When the voltage is not precharged to the correct level, the operation of the sense amplifier (SA) 3 becomes unstable, and this may cause an erroneous read operation. In order to obtain the correct precharge level, the voltage of a boosted bit line needs to be decreased to the VDL level to prevent the voltage in the bit line from being excessively boosted.
In FIG. 6, the waveforms of successive write operations in the case of the tRCD LONG are described. The tRCD LONG includes the tRCD plus a margin. Write operations may be performed after the tRCD LONG or tRCD MINIMUM.
(1) At the time when write operations are performed after the tRCD MINIMUM, the sense amplifier (SA) 3 is activated, and amplification is being performed in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3.
(2) At the time when write operations are performed after the tRCD LONG, sufficient time has elapsed since the sense amplifier (SA) 3 was activated. Thus, the voltage difference in the other parts of the pair of the bit lines BIT T and BIT N far from the sense amplifier (SA) 3 is also sufficient.
(1) Even in the case of the tRCD MINIMUM, the sense amplifier (SA) 3 is overdriven to reduce the tRCD. Since a voltage that is equal to or more than the internal voltage VDL is applied to the sense amplifier (SA) 3, the level that needs to be inverted by the write amplifier WAMP 6 is higher than the internal voltage VDL. Thus, in a write operation with the internal voltage VDL, it may be the case that the write amplifier WAMP 6 cannot invert the bit lines BIT T and BIT N sufficiently, which are amplified by the sense amplifier (SA) 3 operating in an overdrive mode, to write data. In this case, after a corresponding column selection switch YSW is closed, the voltage difference in the bit lines BIT T and BIT N in the sense amplifier (SA) 3 is not sufficient. Thus, subsequently, a delay occurs in the sense amplifier (SA) 3 (in a restore operation) and amplification in the bit lines BIT T and BIT N. Accordingly, a write operation by the overdrive method needs to be performed by the write amplifier WAMP 6. In the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted, as described above.
(2) In the case of the tRCD LONG, the operation is as described above. During the tRCD plus a margin, the write amplifier WAMP 6 is overdriven to quickly invert the bit lines BIT T and BIT N sufficiently amplified by the sense amplifier (SA) 3 to write data. In this way, when a write operation is performed after either the tRCD LONG or the tRCD MINIMUM, the write amplifier WAMP 6 is overdriven to achieve high-speed processing. However, in the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted.
In this way, in the overdrive write method using the power supply voltage VEXT, a problem exists in that the bit line voltage is excessively boosted when successive write operations are performed. Moreover, another problem exists in that, when the bit line voltage is excessively boosted, a correct reference level cannot be obtained in a precharge operation, thereby causing an erroneous operation of the sense amplifier (SA) 3. In International Publication No. WO97/24729 and Japanese Unexamined Patent Application Publication No. 10-255470, the problem that the bit line voltage is excessively boosted, which was found by the inventor, is not described and not recognized. Thus, no technique for solving the problem is suggested.
When successive write operations are repeated on the same word line, an overdrive operation is repeated on bit lines in which a sufficient voltage difference is generated by performing amplification. Thus, a problem exists in that the bit line voltage is excessively boosted. When the bit line voltage is excessively boosted, the voltage in one of the complementary bit lines is excessively boosted to a voltage that is equal to or more than the internal voltage VDL. In this status, after a precharge operation in which the complementary bit lines are shorted, a correct reference level cannot be obtained. Thus, a problem exists in that an erroneous operation of the sense amplifier may occur.